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data sheet low skew, 1-to-16 lvcmos/lvttl fanout buffer 83115i 83115i rev b 4/28/15 1 ?2015 integrated device technology, inc. general description the 83115i is a low skew, 1-to-16 lvcmos/ lvttl fanout buffer. the 83115i single-ended clock i nput accepts lvcmos or lvttl input levels. the 83115i operates at full 3.3v supply mode over the industrial temperature range. guaranteed output and part-to-part skew characteristics make the 83115i ideal for those clock distribution applications demanding well defined performance and repeatability. features ? sixteen lvcmos / lvttl outputs, 15 ? output impedance ? one lvcmos / lvttl clock input ? maximum output frequency: 200mhz ? all inputs are 5v tolerant ? output skew: 250ps (maximum) ? part-to-part skew: 800ps (maximum) ? additive phase jitter, rms: 0.20ps (typical) ? full 3.3v operating supply ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package 83115i 28-lead ssop, 150mil 9.9mm x 3.9mm x 1.5mm package body r package top view 1 2 3 4 5 6 7 28 27 26 25 24 23 22 8 9 10 11 12 13 14 21 20 19 18 17 16 15 q15 q14 q13 q12 q11 q10 q9 q8 gnd gnd oe2 oe0 v dd v dd v dd v dd q1 q2 q3 q4 q5 q6 q7 in gnd gnd q0 oe1 oe0 oe2 oe1 oe2 pin assignment 4 4 q15 q14 q13 q12 q11 q10 q9 q8 in q0 q1 q2 q3 q4 q5 q6 q7 oe0 gnd oe1 oe2 v dd block diagram
rev b 4/28/15 2 low skew, 1-to-16 lvcmos/lvttl fanout buffer 83115i data sheet table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 oe1 input pullup output enable pin. when low, forc es outputs q[2:7] to hi-z state. 5v tolerant. lvcmos/lvttl interface levels. see table 3. 2, 3, 4, 7, 8, 11, 12, 13, 16, 17, 18, 21, 22, 25, 26, 27 q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11, q12, q13, q14, q15 output single-ended clock outputs. 15 ? output impedance. lvcmos/lvttl interface levels. 5, 6, 23, 24 v dd power positive supply pins. 9, 10, 19, 20 gnd power power supply ground. 14 in input pulldown single-ended clock input. 5v tolerant. lvcmos/lvttl interface levels. 15 oe0 input pullup output enable pin. when low, forces outputs q[8:13] to hi-z state. 5v tolerant. lvcmos/lvttl interface levels. see table 3. 28 oe2 input pullup output enable pin. when low, forces outputs q[0:1] and q[14:15] to hi-z state. 5v tolerant. lvcmos/lvttl interface levels. see table 3. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? c pd power dissipation capacitance (per output); note 1 v dd = 3.465v 11 pf r out output impedance v dd = 3.3v 15 ?
low skew, 1-to-16 lvcmos/lvttl fanout buffer 3 rev b 4/28/15 83115i data sheet function tables table 3. oex function table absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c inputs outputs oe0 oe1 oe2 control oe2 q[0:1], q[14:15] control oe1 q[2:7] control oe0 q[8:13] 000hi-zhi-zhi-z 0 0 1 active hi-z hi-z 0 1 0 hi-z active hi-z 0 1 1 active active hi-z 1 0 0 hi-z hi-z active 1 0 1 active hi-z active 1 1 0 hi-z active active 1 1 1 active active active item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ? ja 49 ? c/w (0 lfpm) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current 50 ma
rev b 4/28/15 4 low skew, 1-to-16 lvcmos/lvttl fanout buffer 83115i data sheet table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c note 1: outputs terminated with 50 ? to v dd /2. see parameter measurement information, output load test circuit diagram. ac electrical characteristics table 5. ac characteristics, v dd = 3.3v 5%, t a = -40c to 85c all parameters measured at f max unless noted otherwise. note 1: measured from v dd /2 of the input to v dd /2 of the output. note 2: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v dd /2. note 3: defined as skew between outputs on different devices oper ating at the same supply voltages and with equal load conditio ns. using the same type of inputs on each device, the outputs are measured at v dd /2. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage oe0:oe2 2 v dd + 0.3 v in 2 v dd + 0.3 v v il input low voltage oe0:oe2 -0.3 0.8 v in -0.3 1.3 v i ih input high current oe0:oe2 v dd = v in = 3.465v 5 a in v dd = v in = 3.465v 150 a i il input low current oe0:oe2 v dd = 3.465v, v in = 0v -150 a in v dd = 3.465v, v in = 0v -5 a v oh output high voltage; note 1 v dd = 3.3v 5% 2.6 v v ol output low voltage; note 1 v dd = 3.3v 5% 0.5 v i ozl output hi-z current low 5a i ozh output hi-z current high 5a parameter symbol test conditions minimum typical maximum units f max output frequency 200 mhz t jit( buffer additive phase jitter, rms; refer to additive phase jitter section integration range: 12khz ? 20mhz 0.20 ps tp lh propagation delay; note 1 ? ? 200mhz 1.7 2.4 3.1 ns t sk(o) output skew; note 2, 4 measured on the rising edge @ v dd /2 150 250 ps t sk(pp) part-to-part skew; note 3, 4 measured on the rising edge @ v dd /2 800 ps t r / t f output rise/fall time4 20% to 80% 400 800 ps odc output duty cycle 45 55 % t en output enable time 20 ns t dis output disable time 20 ns
low skew, 1-to-16 lvcmos/lvttl fanout buffer 5 rev b 4/28/15 83115i data sheet additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the powe r of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specif ied offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental . when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offs et from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on th e desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specific ations, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. additive phase jitter, rms @ 155.52mhz (12khz to 20mhz) = 0.20ps (typical) 1k 10k 100k 1m 10m 100m offset frequency (hz) ssb phase noise dbc/hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190
rev b 4/28/15 6 low skew, 1-to-16 lvcmos/lvttl fanout buffer 83115i data sheet parameter measureme nt information 3.3v output load ac test circuit part-to-part skew output rise/fall time output skew propagation delay output duty cycle/pulse width/period scope qx gnd v dd 1.65v5% -1.65v5% - t sk(pp) v dd 2 v dd 2 part 1 part 2 qx qy 20% 80% 80% 20% t r t f q0:q15 t sk(o) qx qy q0:q15 clk t period t pw t period odc = v ddo 2 x 100% t pw q0:q15
low skew, 1-to-16 lvcmos/lvttl fanout buffer 7 rev b 4/28/15 83115i data sheet application information recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos output can be left floating. there should be no trace attached. reliability information table 6. ? ja vs. air flow table for a 28 lead ssop, 150mil transistor count the transistor count for 83115i: 985 ? ja vs. air flow linear feet per minute 0200500 multi-layer pcb, jedec standard test boards 49c/w 36c/w 30c/w
rev b 4/28/15 8 low skew, 1-to-16 lvcmos/lvttl fanout buffer 83115i data sheet package outline and package dimension package outline - g suffix for 28 lead ssop table 7. package dimensions for 28 lead ssop reference document: jedec publication 95, mo-137 all dimensions in millimeters symbol minimum maximum n 28 a 1.35 1.75 a1 0.10 0.25 a2 1.50 b 0.20 0.30 c 0.18 0.25 d 9.80 10.00 e 5.80 6.20 e1 3.80 4.00 e 0.635 basic l 0.40 1.27 ? 0 8 zd 0.84 ref
low skew, 1-to-16 lvcmos/lvttl fanout buffer 9 rev b 4/28/15 83115i data sheet ordering information table 8. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 83115BRILF 83115BRILF ?lead-free? 28 lead ssop tube -40 ? c to 85 ? c 83115BRILFt 83115BRILF ?lead-free? 28 lead ssop tape & reel -40 ? c to 85 ? c
rev b 4/28/15 10 low skew, 1-to-16 lvcmos/lvttl fanout buffer 83115i data sheet revision history sheet rev table page description of change date b t5 4 ac characteristics table - changed output rise/fall time limits from 650ps min./1150ps max. to 400ps min./800ps max. 3/19/08 b t8 9 ordering information - removed leaded devices. updated data sheet format. 4/28/15
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